From the aspect of the design of integrated circuits, the technique of shallow trench isolation has several advantages in manufacturing processes and electrical isolation as compared with that of local oxidation of silicon (LOCOS), and accordingly becomes one of the main stream techniques after the era of line width narrower than 0.25 micron.
Generally, shallow trench isolations (STIs) are used to separate and isolate active areas on a semiconductor wafer from each other. These STIs have historically been formed by etching trenches, overfilling the trenches with a dielectric such as an oxide, and then removing any excess dielectric with a process such as chemical mechanical polishing (CMP) or etching in order to remove the dielectric outside the trenches. This dielectric helps to electrically isolate the active areas from each other.
Since the width of the trench in the STI is quite narrow, currently polysilazane is formed over the semiconductor wafer by the reaction of trisilylamine (a precursor), i.e. N(SiH3)3, oxygen, i.e. O2, and ammonia gas, i.e. NH3 under plasma treatment due to better flowability of polysilazane over oxide, and then the polysilazane is converted into oxide to provide the isolation.
However, the reaction of trisilylamine, oxygen and ammonia gas under the plasma treatment is quite violent, and accordingly the occurrence of defects, e.g. voids, in the polysilazane layer typically can not be avoided. These defects frequently result in the failure of isolation for line widths approaching nanometer scale. Hence, there is a need to solve the above problems.